25 lines
1.1 KiB
Markdown
25 lines
1.1 KiB
Markdown
# Icarus Verilog — UVM Experimental Track
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> **Experimental / research project.** Not for production or tapeout.
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> This is **not** an official Accellera UVM port.
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> **Do not open pull requests to [steveicarus/iverilog](https://github.com/steveicarus/iverilog) for this UVM track.**
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This repository is `muhammadjawadkhan/iverilog-uvm`: a full Icarus Verilog tree plus a UVM-oriented layer under [`uvm/`](uvm/) and a feature roadmap under [`docs/`](docs/).
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| Remote | Role |
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| `origin` | `muhammadjawadkhan/iverilog-uvm` (push here) |
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| `upstream` | `steveicarus/iverilog` (**fetch/merge only** — never PR UVM work there) |
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## Quick links
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- [docs/ROADMAP.md](docs/ROADMAP.md) — SV/UVM features to add one by one
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- [docs/STATUS.md](docs/STATUS.md) — what works today
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- [docs/WORKFLOW.md](docs/WORKFLOW.md) — branch / PR rules for this fork
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- [examples/hello_uvm](examples/hello_uvm) — smoke example using `uvm/`
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- Upstream Icarus build docs: see [README.md](README.md)
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## Goal
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Grow SystemVerilog compiler support and a UVM-like / Accellera-shaped library **in this fork only**, feature by feature, until larger slices of UVM 1.2 become viable.
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