e263d5b268
The operator assignment on dynamic part selects uses the `%store/vec4` instruction to store the value. This instruction will skip the assignment if flag 4 is set. This is for handling the case where the index is undefined. Since the left hand side of the assignment is an arbitrary expression it can change the flag. The implementation handles this by making a copy of the flag and restoring it before executing the `%store/vec4` instruction. The flag is set by the `%ix/vec4` instruction when loading the index register. But the copy of the flag is made before that and just picks up the flag that was stored by previous expressions. This can cause the store to be skipped when it shouldn't. E.g. in the following code the increment will be skipped. Flag 4 is used from the `a == 0` comparison, rather than from computing the part select index. ``` int a = 0; if (a == 0) begin a[a+:2] += 1; end $display(a); // Will print 0, should print 1 ``` Fix this by moving the copy of the flag after the `%ix/vec4` instruction. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| .. | ||
| COPYING.lesser | ||
| Makefile.in | ||
| README.txt | ||
| cppcheck.sup | ||
| draw_class.c | ||
| draw_delay.c | ||
| draw_enum.c | ||
| draw_mux.c | ||
| draw_net_input.c | ||
| draw_substitute.c | ||
| draw_switch.c | ||
| draw_ufunc.c | ||
| draw_vpi.c | ||
| eval_condit.c | ||
| eval_expr.c | ||
| eval_object.c | ||
| eval_real.c | ||
| eval_string.c | ||
| eval_vec4.c | ||
| modpath.c | ||
| stmt_assign.c | ||
| vvp-s.conf.in | ||
| vvp.c | ||
| vvp.conf.in | ||
| vvp_config.h.in | ||
| vvp_priv.h | ||
| vvp_process.c | ||
| vvp_scope.c | ||
README.txt
THE VVP TARGET SYMBOL NAME CONVENTIONS There are some naming conventions that the vvp target uses for generating symbol names. * wires and regs Nets and variables are named V_<full-name> where <full-name> is the full hierarchical name of the signal. * Logic devices Logic devices (and, or, buf, bufz, etc.) are named L_<full_name>. In this case the symbol is attached to a functor that is the output of the logic device. GENERAL FUNCTOR WEB STRUCTURE The net of gates, signals and resolvers is formed from the input design. The basic structure is wrapped around the nexus, which is represented by the ivl_nexus_t. Each nexus represents a resolved value. The input of the nexus is fed by a single driver. If the nexus in the design has multiple drivers, the drivers are first fed into a resolver (or a tree of resolvers) to form a single output that is the nexus. The nexus, then, feeds its output to the inputs of other gates, or to the .net objects in the design.