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iverilog/tgt-vhdl
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Nick Gasson dea54df71b Catch possibly NULL return value 
This is caused by using a hierarchical reference (which can't
be translated to VHDL). The result of get_decl is NULL since
the signal has been declared in a different VHDL architecture.
Adding the assert is cleaner than having it segfault, for the
moment, until a nicer error message can be added.
 		2008-08-12 09:47:03 +01:00
..
vhpi Move the VHDL support package 2008-07-07 15:36:13 +01:00
Makefile.in Split logic device code into separate file 2008-07-30 10:13:08 +01:00
cast.cc Generate combined input for UDP devices 2008-08-11 12:58:46 +01:00
configure.in Makefile and autoconf changes to build VHDL code generator 2008-05-28 17:17:39 +01:00
display.cc Handle %% in $display 2008-08-08 20:07:22 +01:00
expr.cc Division and modulus operators 2008-08-07 14:18:26 +01:00
logic.cc Fix regression caused by UDP delay patch 2008-08-11 20:53:13 +01:00
lpm.cc Division and modulus operators 2008-08-07 14:18:26 +01:00
process.cc Use ivl_process_* functions for file/line number information 2008-08-02 10:44:03 +01:00
scope.cc Change `out' ports to `buffer' when the signal is read 2008-08-11 20:48:28 +01:00
stmt.cc Catch possibly NULL return value 2008-08-12 09:47:03 +01:00
support.cc Always user Ternary_* support functions for ternary assignments 2008-08-02 15:46:36 +01:00
support.hh Conversion of std_logic to integer 2008-07-28 22:46:39 +01:00
vhdl.cc Finish re-writing nexus code 2008-07-29 19:33:40 +01:00
vhdl.conf Makefile and autoconf changes to build VHDL code generator 2008-05-28 17:17:39 +01:00
vhdl_config.h.in Makefile and autoconf changes to build VHDL code generator 2008-05-28 17:17:39 +01:00
vhdl_element.cc Compress support function definitions a bit 2008-07-19 21:04:52 +01:00
vhdl_element.hh Compress support function definitions a bit 2008-07-19 21:04:52 +01:00
vhdl_helper.hh Handle '?' in vl_to_vhdl_bit 2008-08-11 13:53:42 +01:00
vhdl_syntax.cc Change `out' ports to `buffer' when the signal is read 2008-08-11 20:48:28 +01:00
vhdl_syntax.hh Change `out' ports to `buffer' when the signal is read 2008-08-11 20:48:28 +01:00
vhdl_target.h Avoid generating useless `wait for 0ns' statements 2008-08-05 11:02:36 +01:00
vhdl_type.cc Generate VHDL array type declarations of Verilog arrays 2008-07-17 13:08:55 +01:00
vhdl_type.hh Generate VHDL array type declarations of Verilog arrays 2008-07-17 13:08:55 +01:00