iverilog/tgt-vvp
steve de8c725890 Mingw32 support (Venkat Iyer) 2001-05-20 15:09:39 +00:00
..
.cvsignore Add the tgt-vvp code generator target. 2001-03-19 01:20:46 +00:00
Makefile.in Mingw32 support (Venkat Iyer) 2001-05-20 15:09:39 +00:00
README.txt Add a README for notes about the vvp target. 2001-03-25 18:10:39 +00:00
configure.in Mingw32 support (Venkat Iyer) 2001-05-20 15:09:39 +00:00
eval_expr.c Implement reduction nor. 2001-05-20 01:18:38 +00:00
vvp.c Mingw32 support (Venkat Iyer) 2001-05-20 15:09:39 +00:00
vvp_priv.h Behavioral ternary operators for vvp. 2001-05-17 04:37:02 +00:00
vvp_process.c Behavioral ternary operators for vvp. 2001-05-17 04:37:02 +00:00
vvp_scope.c Fixup the resolver syntax. 2001-05-12 16:34:47 +00:00

README.txt

THE VVP TARGET

SYMBOL NAME CONVENTIONS

There are some naming conventions that the vp target uses for
generating symbol names.

* wires and regs

Nets and variables are named V_<full-name> where <full-name> is the
full hierarchical name of the signal.

* Logic devices

Logic devices (and, or, buf, bufz, etc.) are named L_<full_name>. In
this case the symbol is attached to a functor that is the output of
the logic device.