Stephen Williams 73dcace781 Prevent macro expand in strings, and add a stringify syntax ... Verilog does not allow macro expansion in strings, and that's that. But sometimes people want strings of a macro expansion, so add a stringify syntax that does the trick.		2008-05-08 18:43:07 -07:00
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.cvsignore	ivlpp: Removed the unnecessary parser	2008-02-19 09:31:02 -08:00
Makefile.in	ivlpp: Removed the unnecessary parser	2008-02-19 09:31:02 -08:00
globals.h	ivlpp: Removed the unnecessary parser	2008-02-19 09:31:02 -08:00
ivlpp.txt	Spelling fixes	2008-01-29 20:24:24 -08:00
lexor.lex	Prevent macro expand in strings, and add a stringify syntax	2008-05-08 18:43:07 -07:00
main.c	Ignore a few more compiler directives.	2008-04-27 21:18:21 -07:00