mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-01 02:07:42 +02:00
Flavien SoltandClaude Opus 4.8
c53e4245b9
Check that the vvp code generator emits a -0.0 real constant with its sign bit set, so the compiled value matches the runtime real value. The sign used to be detected with (value < 0), which is false for IEEE 754 -0.0, and a -0.0 constant was turned into +0.0. Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>
5 lines
67 B
JSON
5 lines
67 B
JSON
{
|
|
"type" : "normal",
|
|
"source" : "real_negative_zero.v"
|
|
}
|