iverilog/ivtest/vvp_tests/module_ordered_list1.json at 9bbdb0da0ebb2bd2d06fbfbe2cc85629d59cbd6a - iverilog - Gitea: Git with a cup of tea

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Lars-Peter Clausen 37f7308f80 Add regression test for omitting trailing ports in ordered list connection

Check that it is possible to omit trailing ports in a module ordered list
connection list.

Also check that an error is generated if too many ports are specified in a
ordered list connection.

Signed-off-by: Lars-Peter Clausen <[email protected]>

2023-06-11 08:45:34 -07:00

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 {
     "type"          : "normal",
     "source"        : "module_ordered_list1.v",
     "iverilog-args" : [ "-g2005-sv" ]
 }