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Check that synthesized case statement muxes can use array words as inputs. This used to generate invalid VVP because .array/port statements were emitted in the middle of .functor statements. Signed-off-by: Lars-Peter Clausen <[email protected]>
6 lines
100 B
JSON
6 lines
100 B
JSON
{
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"type" : "normal",
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"source" : "case_mux_array_word.v",
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"iverilog-args" : [ "-S" ]
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}
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