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Lars-Peter Clausen
9ffe627b32
Check that the var keyword is supported in the following contexts * Module ports (both ANSI and non-ANSI) * Module variable declarations * Package variable declarations * Task and function ports * block variable declarations * for loop variable declarations Also check that it is an error to use the var keyword in a for loop without an explicit data type, as that is not allowed by the standard. Signed-off-by: Lars-Peter Clausen <[email protected]>
61 lines
1017 B
Verilog
61 lines
1017 B
Verilog
// Check that the var keyword is supported for module non-ANSI input ports
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bit failed = 1'b0;
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`define check(val, exp) \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, `"val`", val, exp); \
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failed = 1'b1; \
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end
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module M(x, y, z, w);
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parameter VAL_X = 0;
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parameter VAL_Y = 0;
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parameter VAL_Z = 0;
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parameter VAL_W = 0;
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input var x;
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input var [7:0] y;
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input var signed [7:0] z;
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input var logic [7:0] w;
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initial begin
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`check(x, VAL_X)
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`check(y, VAL_Y)
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`check(z, VAL_Z)
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`check(w, VAL_W)
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end
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endmodule
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module test;
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M #(
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.VAL_X (1'b1),
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.VAL_Y (8'd10),
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.VAL_Z (-8'sd1),
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.VAL_W (8'd20)
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) i_m1 (
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.x (1'b1),
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.y (8'd10),
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.z (-8'sd1),
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.w (8'd20)
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);
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// When unconnected it should default to x, rather z
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M #(
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.VAL_X (1'bx),
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.VAL_Y (8'hx),
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.VAL_Z (8'hx),
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.VAL_W (8'hx)
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) i_m2 ();
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initial begin
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#1
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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