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Lars-Peter Clausen
28e121c040
Check that SystemVerilog net declarations can mix entries with and without initialization. Check that in SystemVerilog it is possible to do assignments within net array declarations. Signed-off-by: Lars-Peter Clausen <[email protected]>
28 lines
484 B
Verilog
28 lines
484 B
Verilog
// Check that net arrays can be initialized during declaration.
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module test;
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reg failed;
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wire [3:0] a[0:1] = '{4'h1, 4'h2};
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`define check(val, exp) \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, \
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`"val`", exp, val); \
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failed = 1'b1; \
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end
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initial begin
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failed = 1'b0;
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`check(a[0], 4'h1)
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`check(a[1], 4'h2)
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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