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These test verify that explicit cast to packed array and packed struct types are supported and executed correctly. The tests are based on the test for integer casts. Just the type of the variables was changed to packed array and packed struct respectively. Signed-off-by: Lars-Peter Clausen <[email protected]>
44 lines
2.0 KiB
Verilog
44 lines
2.0 KiB
Verilog
// This tests SystemVerilog casting support
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Iztok Jeras.
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// Extended by Maciej Suminski
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// Copied and modified by Martin Whitaker
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// Copied and modified again by Lars-Peter Clausen
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module test();
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typedef logic [7:0] pa08;
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typedef pa08 [1:0] pa16;
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typedef pa16 [1:0] pa32;
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typedef pa32 [1:0] pa64;
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// variables used in casting
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pa08 var_08;
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pa16 var_16;
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pa32 var_32;
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pa64 var_64;
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real var_real;
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// error counter
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bit err = 0;
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initial begin
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var_08 = pa08'(4'h5); if (var_08 !== 8'h05) begin $display("FAILED -- var_08 = 'h%0h != 8'h05", var_08); err=1; end
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var_16 = pa16'(var_08); if (var_16 !== 16'h05) begin $display("FAILED -- var_16 = 'h%0h != 16'h05", var_16); err=1; end
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var_32 = pa32'(var_16); if (var_32 !== 32'h05) begin $display("FAILED -- var_32 = 'h%0h != 32'h05", var_32); err=1; end
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var_64 = pa64'(var_32); if (var_64 !== 64'h05) begin $display("FAILED -- var_64 = 'h%0h != 64'h05", var_64); err=1; end
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var_real = 13.4; var_08 = pa08'(var_real); if (var_08 !== 13) begin $display("FAILED -- var_08 = %d != 13", var_08); err=1; end
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var_real = 14.5; var_16 = pa16'(var_real); if (var_16 !== 15) begin $display("FAILED -- var_16 = %d != 15", var_16); err=1; end
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var_real = 15.6; var_32 = pa32'(var_real); if (var_32 !== 16) begin $display("FAILED -- var_32 = %d != 16", var_32); err=1; end
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var_real = -15.6; var_64 = pa64'(var_real); if (var_64 !== -16) begin $display("FAILED -- var_64 = %d != -16", var_64); err=1; end
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var_08 = pa08'(4'hf); if (var_08 !== 8'h0f) begin $display("FAILED -- var_08 = 'h%0h != 8'h0f", var_08); err=1; end
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var_16 = pa08'(16'h0f0f); if (var_16 !== 16'h0f) begin $display("FAILED -- var_16 = 'h%0h != 16'h0f", var_16); err=1; end
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if (!err) $display("PASSED");
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end
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endmodule // test
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