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https://github.com/steveicarus/iverilog.git
synced 2026-09-03 16:29:25 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
41 lines
537 B
Verilog
41 lines
537 B
Verilog
module recursive_task();
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task automatic factorial;
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input integer n;
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output integer f;
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integer t;
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fork
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begin
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if (n > 1)
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factorial(n - 1, t);
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else
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t = 1;
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#1 f = n * t;
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end
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begin
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@f $display("intermediate value = %0d", f);
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end
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join
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endtask
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integer r1;
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integer r2;
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integer r3;
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initial begin
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fork
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factorial(3, r1);
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factorial(4, r2);
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factorial(5, r3);
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join
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$display("factorial 3 = %0d", r1);
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$display("factorial 4 = %0d", r2);
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$display("factorial 5 = %0d", r3);
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end
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endmodule
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