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Flavien SoltandClaude Opus 4.8
c53e4245b9
Check that the vvp code generator emits a -0.0 real constant with its sign bit set, so the compiled value matches the runtime real value. The sign used to be detected with (value < 0), which is false for IEEE 754 -0.0, and a -0.0 constant was turned into +0.0. Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>
36 lines
936 B
Verilog
36 lines
936 B
Verilog
// Check that the vvp code generator preserves the sign of a negative zero
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// real constant. The sign used to be detected with (value < 0), which is
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// false for IEEE 754 -0.0, so a -0.0 constant was emitted as +0.0 and the
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// compiled value no longer matched the runtime real value.
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module test;
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real nz;
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real pz;
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initial begin
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nz = -0.0;
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pz = 0.0;
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// The sign bit is the only thing that tells -0.0 from +0.0.
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if ($realtobits(nz) !== 64'h8000_0000_0000_0000) begin
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$display("FAILED: -0.0 stored as %h", $realtobits(nz));
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$finish;
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end
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if ($realtobits(pz) !== 64'h0000_0000_0000_0000) begin
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$display("FAILED: 0.0 stored as %h", $realtobits(pz));
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$finish;
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end
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// The reciprocal makes the sign observable: 1.0/-0.0 is -inf.
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if (1.0 / nz >= 0.0) begin
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$display("FAILED: 1.0/-0.0 = %g", 1.0 / nz);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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