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Lars-Peter Clausen
8519a30354
Check that assignment patterns cannot be connected directly to unpacked array output ports. Signed-off-by: Lars-Peter Clausen <[email protected]>
18 lines
247 B
Verilog
18 lines
247 B
Verilog
// Check that an output array port expression must be assignable.
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module M (
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output int out [0:1]
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);
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initial begin
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out = '{3, 4};
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end
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endmodule
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module test;
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M i_m('{1, 2}); // Error: output expression is not assignable
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endmodule
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