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Lars-Peter Clausen
37f7308f80
Check that it is possible to omit trailing ports in a module ordered list connection list. Also check that an error is generated if too many ports are specified in a ordered list connection. Signed-off-by: Lars-Peter Clausen <[email protected]>
25 lines
343 B
Verilog
25 lines
343 B
Verilog
// Check that an error is reported when specifying too many ports in a ordered
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// list connection.
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module M (
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output a,
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input b
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);
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assign a = b;
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endmodule
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module test;
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wire a, b, c;
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assign b = 1'b0;
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assign c = 1'b1;
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M i_M (a, b, c); // Error, too many ports.
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initial begin
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$display("FAILED");
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end
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endmodule
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