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Lars-Peter Clausen
ee81ac2f85
Check that it is possible to define the data type of a non-ANSI module port in a separate declaration from the port direction. Add tests for both the type declared before the port direction and for the type declared after the port direction. Note that this doesn't work yet correctly for integer type module ports yet, so there are no tests for this. This will be addressed in follow up work. Signed-off-by: Lars-Peter Clausen <[email protected]>
17 lines
338 B
Verilog
17 lines
338 B
Verilog
// Check that it is possible to declare the data type for a vector type module
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// port before the direction for non-ANSI style port declarations.
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module test(x);
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reg [7:0] x;
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output [7:0] x;
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initial begin
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if ($bits(x) == 8) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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