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Check that the behavior for all sorts of base types for enums is correctly implemented. Both for valid as well as invalid base types. Signed-off-by: Lars-Peter Clausen <[email protected]>
19 lines
319 B
Verilog
19 lines
319 B
Verilog
// Check that it is possible to declare an enum type without an explicit base
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// type. In this case the base type should default to `int`.
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module test;
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enum {
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A
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} E;
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initial begin
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if ($bits(E) == 32) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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