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iverilog/ivtest/ivltests/enum_base_none.v
T
Lars-Peter Clausen 315bc1908a Add regression tests for enum base type
Check that the behavior for all sorts of base types for enums is correctly
implemented. Both for valid as well as invalid base types.

Signed-off-by: Lars-Peter Clausen <[email protected]>
2022-03-25 21:55:34 +01:00

19 lines
319 B
Verilog

// Check that it is possible to declare an enum type without an explicit base
// type. In this case the base type should default to `int`.
module test;
enum {
A
} E;
initial begin
if ($bits(E) == 32) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule