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16 lines
255 B
Verilog
16 lines
255 B
Verilog
// Github Issue #202
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module main;
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reg clk = 0;
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initial begin
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//$dumpfile("foo"); // We really want to test the command line flag
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$dumpvars(0, main);
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#10 clk <= 1;
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#10 clk <= 0;
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#10 $finish;
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end
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endmodule // main
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