mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-03 08:25:32 +02:00
Lars-Peter Clausen
c4397e66f9
Check that a sign, width or type cast expression that contains an automatic term is detected as such and can not be used as the left-hand side in a procedural continuous assignment. Signed-off-by: Lars-Peter Clausen <[email protected]>
23 lines
349 B
Verilog
23 lines
349 B
Verilog
// Check that an expression is correctly detected to contain an automatic
|
|
// variable if the variable is in a SystemVerilog sign cast expression.
|
|
|
|
module test;
|
|
|
|
reg g;
|
|
|
|
task automatic auto_task;
|
|
reg l;
|
|
|
|
begin: block
|
|
assign g = signed'(l);
|
|
end
|
|
|
|
endtask
|
|
|
|
initial begin
|
|
auto_task;
|
|
$display("FAILED");
|
|
end
|
|
|
|
endmodule
|