mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-03 06:43:22 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
69 lines
1.5 KiB
Verilog
69 lines
1.5 KiB
Verilog
// Check behaviour with out-of-range and undefined array indices
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// on LHS of continuous assignment.
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`ifdef __ICARUS__
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`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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`define SUPPORT_REAL_NETS_IN_IVTEST
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`endif
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module top;
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wire [1:0] array1[2:1];
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wire [1:0] array2[1:0];
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`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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assign array1[0] = 2'd0;
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`endif
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assign array1[1] = 2'd1;
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assign array1[2] = 2'd2;
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`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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assign array1[3] = 2'd3;
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`endif
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assign array2[0] = 2'd0;
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assign array2[1] = 2'd1;
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`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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assign array2['bx] = 2'd2;
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`endif
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`ifdef SUPPORT_REAL_NETS_IN_IVTEST
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wire real array3[2:1];
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wire real array4[1:0];
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assign array3[0] = 0.0;
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assign array3[1] = 1.0;
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assign array3[2] = 2.0;
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assign array3[3] = 3.0;
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assign array4[0] = 0.0;
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assign array4[1] = 1.0;
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assign array4['bx] = 2.0;
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`endif
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reg failed;
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initial begin
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#1 failed = 0;
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$display("array = %h %h", array1[2], array1[1]);
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if ((array1[1] !== 2'd1) || (array1[2] !== 2'd2)) failed = 1;
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$display("array = %h %h", array2[1], array2[0]);
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if ((array2[0] !== 2'd0) || (array2[1] !== 2'd1)) failed = 1;
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`ifdef SUPPORT_REAL_NETS_IN_IVTEST
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$display("array = %0g %0g", array3[2], array3[1]);
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if ((array3[1] != 1.0) || (array3[2] != 2.0)) failed = 1;
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$display("array = %0g %0g", array4[1], array4[0]);
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if ((array4[0] != 0.0) || (array4[1] != 1.0)) failed = 1;
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`endif
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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