SystemVerilog allows fewer actual arguments than formal arguments when all remaining formal arguments have default values. |
||
|---|---|---|
| .. | ||
| Makefile.in | ||
| globals.h | ||
| ivlpp.txt | ||
| lexor.lex | ||
| main.c | ||
SystemVerilog allows fewer actual arguments than formal arguments when all remaining formal arguments have default values. |
||
|---|---|---|
| .. | ||
| Makefile.in | ||
| globals.h | ||
| ivlpp.txt | ||
| lexor.lex | ||
| main.c | ||