iverilog/vhdlpp
Stephen Williams 9b816f6478 Add support for nested when/else expressions. 2012-05-22 17:31:25 -07:00
..
Makefile.in Update lex/yacc builds to be consistent and to support parallel builds 2012-01-04 18:21:40 -08:00
README.txt Spelling fixes to vhdlpp tree 2012-05-17 16:42:03 -07:00
architec.cc Initial support for if_generate syntax. 2012-05-22 17:31:25 -07:00
architec.h Initial support for if_generate syntax. 2012-05-22 17:31:25 -07:00
architec_debug.cc Add support for VHDL for-generate 2011-10-30 17:10:19 -07:00
architec_elaborate.cc Initial support for if_generate syntax. 2012-05-22 17:31:25 -07:00
architec_emit.cc Initial support for if_generate syntax. 2012-05-22 17:31:25 -07:00
compiler.cc Add file/line information to entities and ports 2011-01-18 17:03:51 -08:00
compiler.h Add VHDL support for named libraries 2011-07-30 15:04:07 -07:00
debug.cc Add support for nested when/else expressions. 2012-05-22 17:31:25 -07:00
entity.cc Put off array bound evaluation / describe entity generics as parameters 2011-10-15 17:41:48 -07:00
entity.h Spelling fixes to vhdlpp tree 2012-05-17 16:42:03 -07:00
entity_elaborate.cc Elaborate expressions for entity generics. 2011-10-29 17:07:03 -07:00
entity_emit.cc Get parameter output syntax right for vhdlpp. 2011-10-16 11:01:32 -07:00
entity_stream.cc Write package headers to a library file 2011-07-19 19:19:27 -07:00
expression.cc Add support for nested when/else expressions. 2012-05-22 17:31:25 -07:00
expression.h Add support for nested when/else expressions. 2012-05-22 17:31:25 -07:00
expression_elaborate.cc Add support for nested when/else expressions. 2012-05-22 17:31:25 -07:00
expression_emit.cc Add support for nested when/else expressions. 2012-05-22 17:31:25 -07:00
expression_evaluate.cc Put off array bound evaluation / describe entity generics as parameters 2011-10-15 17:41:48 -07:00
expression_stream.cc Support write_to_stream for arithmetic expressions. 2011-11-05 15:55:41 -07:00
ivl_assert.h Distinguish bit selects of entity ports from function calls. 2011-09-11 15:28:58 -07:00
lexor.lex Spelling fixes to vhdlpp tree 2012-05-17 16:42:03 -07:00
lexor_keyword.gperf properly handle vhdl open ports in component instantiations. 2011-06-12 16:59:07 -07:00
library.cc Support types in packages. 2012-05-22 17:31:25 -07:00
main.cc Use mkdir() instead of _mkdir() for MinGW 2011-12-18 11:43:35 -08:00
package.cc Support types in packages. 2012-05-22 17:31:25 -07:00
package.h Write package headers to a library file 2011-07-19 19:19:27 -07:00
parse.y Add support for nested when/else expressions. 2012-05-22 17:31:25 -07:00
parse_api.h Spelling fixes to vhdlpp tree 2012-05-17 16:42:03 -07:00
parse_misc.cc Put off array bound evaluation / describe entity generics as parameters 2011-10-15 17:41:48 -07:00
parse_misc.h Support types in packages. 2012-05-22 17:31:25 -07:00
parse_types.h Support VHDL user defined array types. 2011-11-05 15:55:17 -07:00
parse_wrap.h Parse/decorate sequential statements. 2011-05-08 16:40:35 -07:00
scope.cc Support types in packages. 2012-05-22 17:31:25 -07:00
scope.h Support types in packages. 2012-05-22 17:31:25 -07:00
sequential.cc Support VHDL user defined array types. 2011-11-05 15:55:17 -07:00
sequential.h Support VHDL user defined array types. 2011-11-05 15:55:17 -07:00
sequential_debug.cc Elaborate and emit case statements. 2011-10-01 11:45:28 -07:00
sequential_elaborate.cc Elaborate and emit case statements. 2011-10-01 11:45:28 -07:00
sequential_emit.cc Put off array bound evaluation / describe entity generics as parameters 2011-10-15 17:41:48 -07:00
vhdlint.cc Remove clang/clang++ warnings. 2011-09-25 10:14:04 -07:00
vhdlint.h Remove clang/clang++ warnings. 2011-09-25 10:14:04 -07:00
vhdlnum.h Introductory changes for numbers handling 2011-02-10 18:34:13 -08:00
vhdlpp_config.h.in Introduce shell of vhdlpp program. 2011-01-18 17:03:51 -08:00
vhdlreal.cc Fix spacing problems. 2011-03-03 11:21:31 -08:00
vhdlreal.h Fix spacing problems. 2011-03-03 11:21:31 -08:00
vsignal.cc VHDL initialization expressions for signals. 2011-10-29 17:06:40 -07:00
vsignal.h VHDL initialization expressions for signals. 2011-10-29 17:06:40 -07:00
vtype.cc Move some VType::show methods to ::write_to_stream methods. 2012-05-22 17:31:25 -07:00
vtype.h Move some VType::show methods to ::write_to_stream methods. 2012-05-22 17:31:25 -07:00
vtype_emit.cc Parse record types, and some new aggregate types. 2012-05-22 17:31:25 -07:00
vtype_stream.cc Support types in packages. 2012-05-22 17:31:25 -07:00

README.txt

vhdlpp COMMAND LINE FLAGS:

-D <token>
  Debug flags. The token can be:

  * yydebug | no-yydebug

  * entities=<path>

-L <path>
  Library path. Add the directory name to the front of the library
  search path. The library search path is initially empty.

-V
  Display version on stdout

-v
  Verbose: Display version on stderr, and enable verbose messages to
  stderr.

-w <path>
  Work path. This is the directory where the working directory is.


LIBRARY FORMAT:

The vhdlpp program stores libraries as directory that contain
packages. The name of the directory (in lower case) is the name of the
library as used on the "import" statement. Within that library, there
are packages in files named <foo>.pkg. For example:

    <directory>/...
       sample/...
         test1.pkg
	 test2.pkg
       bar/...
         test3.pkg

Use the "+vhdl-libdir+<directory>" record in a config file to tell
Icarus Verilog that <directory> is a place to look for libraries. Then
in your VHDL code, access packages like this:

    library sample;
    library bar;
    use sample.test1.all;
    use bar.test3.all;

The *.pkg files are just VHDL code containing only the package with
the same name. When Icarus Verilog encounters the "use <lib>.<name>.*;"
statement, it looks for the <name>.pkg file in the <lib> library and
parses that file to get the package header declared therein.