mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-30 01:28:30 +02:00
Stephen Williams
5aa810dde7
Put together the infrastructure for elaborating analog statements, including create the NetAnalogTop objects that hold analog statements and are in turn held by the design. While doing this, clean up the various unique initial/always enumerations to use the ivl_process_type_t type.
64 lines
1.7 KiB
C++
64 lines
1.7 KiB
C++
/*
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* Copyright (c) 2002-2008 Stephen Williams ([email protected])
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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# include "config.h"
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# include "functor.h"
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# include "netlist.h"
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# include <assert.h>
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/*
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* Most process statements are not roots of synchronous logic.
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*/
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bool NetProc::is_synchronous()
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{
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return false;
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}
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bool NetEvWait::is_synchronous()
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{
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for (unsigned idx = 0 ; idx < nevents_ ; idx += 1) {
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NetEvent*ev = events_[idx];
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if (ev->nprobe() == 0)
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return false;
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for (unsigned pdx = 0 ; pdx < ev->nprobe() ; pdx += 1) {
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NetEvProbe*pr = ev->probe(pdx);
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/* No level sensitive clocks. */
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if (pr->edge() == NetEvProbe::ANYEDGE)
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return false;
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}
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}
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/* So we know that there is a clock source. Check that the
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input to the storage is asynchronous. */
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return true; //statement_->is_asynchronous();
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}
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bool NetProcTop::is_synchronous()
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{
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if (type_ == IVL_PR_INITIAL)
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return false;
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return statement_->is_synchronous();
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}
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