mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-30 09:38:35 +02:00
Stephen Williams
5aa810dde7
Put together the infrastructure for elaborating analog statements, including create the NetAnalogTop objects that hold analog statements and are in turn held by the design. While doing this, clean up the various unique initial/always enumerations to use the ivl_process_type_t type.
92 lines
2.5 KiB
C++
92 lines
2.5 KiB
C++
/*
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* Copyright (c) 2002-2008 Stephen Williams ([email protected])
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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# include "config.h"
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# include "functor.h"
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# include "netlist.h"
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# include <assert.h>
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bool NetAssign::is_asynchronous()
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{
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return true;
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}
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bool NetCondit::is_asynchronous()
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{
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return false;
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}
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/*
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* NetEvWait statements come from statements of the form @(...) in the
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* Verilog source. These event waits are considered asynchronous if
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* all of the events in the list are ANYEDGE, and all the inputs to
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* the statement are included in the sensitivity list. If any of the
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* events are posedge or negedge, the statement is synchronous
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* (i.e. an edge-triggered flip-flop) and if any of the inputs are
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* unaccounted for in the sensitivity list then the statement is a
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* latch.
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*/
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bool NetEvWait::is_asynchronous()
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{
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/* The "sense" set contains the set of Nexa that are in the
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sensitivity list. We also require that the events are all
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level sensitive, but the nex_async_ method takes care of
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that test. */
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NexusSet*sense = new NexusSet;
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for (unsigned idx = 0 ; idx < nevents_ ; idx += 1) {
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NexusSet*tmp = event(idx)->nex_async_();
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if (tmp == 0) {
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delete sense;
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return false;
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}
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sense->add(*tmp);
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delete tmp;
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}
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NexusSet*inputs = statement_->nex_input();
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if (! sense->contains(*inputs)) {
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delete sense;
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delete inputs;
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return false;
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}
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delete sense;
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delete inputs;
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/* If it passes all the other tests, then this statement is
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asynchronous. */
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return true;
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}
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bool NetProc::is_asynchronous()
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{
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return false;
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}
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bool NetProcTop::is_asynchronous()
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{
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if (type_ == IVL_PR_INITIAL)
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return false;
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return statement_->is_asynchronous();
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}
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