45 lines
1.9 KiB
Markdown
45 lines
1.9 KiB
Markdown
# Welcome to *IVL_UVM* project
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It is a humble attempt to implement some of the basic UVM features on open-source Icarus Verilog simulator and eventually port it to Verilator as well.
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Given the light-weight support of SystemVerilog by Icarus as of Dec 2020, IVL_UVM code base is also very rudimentary compared to Accellera UVM implementation. We hope to continue enhancing it as and when the Icarus SV support improves.
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It is very important to note that current support is *very, very limited* and is just a start. We have staretd with:
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* Basic Messaging support
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* Command Line Processor features
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* UVM Test feature
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Feel free to try it out and send constructive comments via Discussion forum/Issues. Any inappropriate comments shall be deleted without any notice whatsoever.
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As of now, IVL_UVM runs on latest/development build of Icarus (and NOT the stable v11.0 branch). Should you need the v11.0 support, feel free to raise a request, we will see if that is doable.
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## Setup
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Please ensure to setup IVL_UVM path via the setup.csh, in CSH/TCSH do:
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* source setup.csh
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Many scripts/Makefiles refer to an env-variable that's set via this setup file.
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To run basic tests, do:
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* cd ivl_uvm_regress/run_dir
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* make vw0
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* make vw1
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* make vw2
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Thanks for trying this IVL_UVM code base.
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## ABV support via OVL
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Assertion Based Verificaiton (ABV) is a powerful technique used by both RTL designers and Verification engineers. Accellera OVL (Open Verificaiton Library) was developed to provide a set of ready-to-use library elements with assertions for common elements/behaviors. We now comppiled OVL with Icarus and did some small clean-up in this release. Further TODOs are below:
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* Integrate UVM reporting
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* Tighter controf of MAX_QUIT_COUNT in more-UVM-like manner (than compile time in old OVL)
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* Better debug
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To run simple OVL demo, do:
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* cd ivl_uvm_tests/ivl_uvm_ovl_demo/ivl_uvm_ovl_alw
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* make
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Cheers
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