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iverilog/tgt-vhdl
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Nick Gasson 72019959a8 Translate some ternary expressions to if statements 
This re-implements some earlier functionality where
ternary expressions on an assignment RHS are translated
to an if statement.
 		2008-08-03 15:47:32 +01:00
..
vhpi Move the VHDL support package 2008-07-07 15:36:13 +01:00
Makefile.in Split logic device code into separate file 2008-07-30 10:13:08 +01:00
cast.cc Conversion of std_logic to integer 2008-07-28 22:46:39 +01:00
configure.in Makefile and autoconf changes to build VHDL code generator 2008-05-28 17:17:39 +01:00
display.cc Catch case of select expression on non-variable 2008-07-24 16:00:12 +01:00
expr.cc Add binary NAND and NOR operators 2008-08-01 17:42:26 +01:00
logic.cc Add NAND and NOR logic devices 2008-08-01 17:46:04 +01:00
lpm.cc Minimal implementation of IVL_LPM_MUX 2008-08-03 12:46:50 +01:00
process.cc Use ivl_process_* functions for file/line number information 2008-08-02 10:44:03 +01:00
scope.cc Add file / line number information to functions 2008-08-03 14:46:57 +01:00
stmt.cc Translate some ternary expressions to if statements 2008-08-03 15:47:32 +01:00
support.cc Always user Ternary_* support functions for ternary assignments 2008-08-02 15:46:36 +01:00
support.hh Conversion of std_logic to integer 2008-07-28 22:46:39 +01:00
verilog_support.vhd Refactor nexus expansion functions. 2008-07-13 15:17:14 +01:00
vhdl.cc Finish re-writing nexus code 2008-07-29 19:33:40 +01:00
vhdl.conf Makefile and autoconf changes to build VHDL code generator 2008-05-28 17:17:39 +01:00
vhdl_config.h.in Makefile and autoconf changes to build VHDL code generator 2008-05-28 17:17:39 +01:00
vhdl_element.cc Compress support function definitions a bit 2008-07-19 21:04:52 +01:00
vhdl_element.hh Compress support function definitions a bit 2008-07-19 21:04:52 +01:00
vhdl_helper.hh Correctly indent case statements 2008-07-23 14:31:41 +01:00
vhdl_syntax.cc Add some whitespace above component instantiations 2008-08-03 14:50:13 +01:00
vhdl_syntax.hh Translate some ternary expressions to if statements 2008-08-03 15:47:32 +01:00
vhdl_target.h Split logic device code into separate file 2008-07-30 10:13:08 +01:00
vhdl_type.cc Generate VHDL array type declarations of Verilog arrays 2008-07-17 13:08:55 +01:00
vhdl_type.hh Generate VHDL array type declarations of Verilog arrays 2008-07-17 13:08:55 +01:00