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Lars-Peter Clausen
521a7bea61
Check that when port direction and data type are declared separately that an error is reported if the port direction has an explicit range specification, but the data type has not. This should even be the case if the data type has an implicit range, e.g `int` or a struct type. For vector types also check that it is an error if the ranges are not identical. Signed-off-by: Lars-Peter Clausen <[email protected]>
14 lines
289 B
Verilog
14 lines
289 B
Verilog
// Check that it is an error to declare a non-ANSI module port with implicit
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// packed dimensions if it is later redeclared as a vector typed variable and
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// the vector type is a scalar.
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module test(x);
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output [7:0] x;
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reg x;
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initial begin
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$display("FAILED");
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end
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endmodule
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