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Lars-Peter Clausen
2acf7aded5
Check that all kinds of invalid module port declarations, where the declaration conflicts with previous declarations, are detected as errors. They should not crash the application nor should they result in successful elaboration. The tests are created for corner cases that previously resulted in incorrect behavior. Signed-off-by: Lars-Peter Clausen <[email protected]>
9 lines
191 B
Verilog
9 lines
191 B
Verilog
// Check that declaring both a net and a variable for a signal that was
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// previously declared as a non-ANSI module port is an error.
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module test(x);
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input x;
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wire x;
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reg x;
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endmodule
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