iverilog/Documentation/developer/guide
Lars-Peter Clausen 5311c0cd38 vvp: Add opcode for unary real minus
Currently the vvp target emits unary real minus as `0.0 - value`.
This is not the same operation for all real values. It loses the
negative zero result for `-(+0.0)` and does not reliably flip the sign
bit for NaN values whose bits are visible through `$realtobits`.

Add `%neg/wr` and use it for unary real minus. This performs a direct
negation of the real stack value, so zero, NaN and infinity all use the
same operation as unary minus instead of a binary subtraction from zero.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2026-06-22 07:43:02 -07:00
..
cadpli Move textfiles to documentation 2023-06-09 13:30:44 +02:00
ivl Move textfiles to documentation 2023-06-09 13:30:44 +02:00
misc Move Icarus Verilog extensions documentation to the usage section. 2024-01-28 17:44:23 +00:00
tgt-vvp Move textfiles to documentation 2023-06-09 13:30:44 +02:00
vpi Update docs Copyright 2024-01-20 18:10:30 -08:00
vvp vvp: Add opcode for unary real minus 2026-06-22 07:43:02 -07:00
index.rst Fix typo: contributer -> contributor 2026-03-05 22:48:57 +01:00