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iverilog/tgt-vhdl
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Nick Gasson 3bd480a375 Allow ouput to be read if connected to child output 
If output P of A is connected to output Q of B (and A is
instantiated inside B) then VHDL does not allow B to read
the value of Q (also P), but Verilog does. To get around
this the output Q is mapped to P_Sig which is then connected
to P, this allows B to read the value of P/Q via P_Sig.
 		2008-07-13 12:41:02 +01:00
..
vhpi Move the VHDL support package 2008-07-07 15:36:13 +01:00
Makefile.in Improved implementation of $display 2008-06-20 11:51:13 +01:00
configure.in Makefile and autoconf changes to build VHDL code generator 2008-05-28 17:17:39 +01:00
display.cc Fix bug with $display and integer literals 2008-06-25 21:54:11 +01:00
expr.cc Change 'signdness' to 'signdness' 2008-07-10 19:27:17 +01:00
lpm.cc Correct vector sizes for bit select 2008-07-08 00:20:31 +01:00
process.cc Fix small bug with initialisation and ammend comments 2008-06-24 20:13:18 +01:00
scope.cc Allow ouput to be read if connected to child output 2008-07-13 12:41:02 +01:00
stmt.cc Bit select bug fixes 2008-07-07 21:19:59 +01:00
verilog_support.vhd Add Active_High support func and fix LPM part select 2008-07-07 16:17:54 +01:00
vhdl.cc Allow ouput to be read if connected to child output 2008-07-13 12:41:02 +01:00
vhdl.conf Makefile and autoconf changes to build VHDL code generator 2008-05-28 17:17:39 +01:00
vhdl_config.h.in Makefile and autoconf changes to build VHDL code generator 2008-05-28 17:17:39 +01:00
vhdl_element.cc Add vhdl_element::print method for debugging 2008-07-01 10:44:20 +01:00
vhdl_element.hh Add vhdl_element::print method for debugging 2008-07-01 10:44:20 +01:00
vhdl_helper.hh Make vhdl_element::emit a little more generic 2008-07-01 10:37:22 +01:00
vhdl_syntax.cc Allow ouput to be read if connected to child output 2008-07-13 12:41:02 +01:00
vhdl_syntax.hh Allow ouput to be read if connected to child output 2008-07-13 12:41:02 +01:00
vhdl_target.h Allow ouput to be read if connected to child output 2008-07-13 12:41:02 +01:00
vhdl_type.cc Correct vector sizes for bit select 2008-07-08 00:20:31 +01:00
vhdl_type.hh Correct vector sizes for bit select 2008-07-08 00:20:31 +01:00