iverilog

History

steve 4d8954be4c Fixup the resolver syntax.		2001-05-12 16:34:47 +00:00
..
.cvsignore	Add the tgt-vvp code generator target.	2001-03-19 01:20:46 +00:00
Makefile.in	Fix compilation warnings.	2001-03-31 19:29:23 +00:00
README.txt	Add a README for notes about the vvp target.	2001-03-25 18:10:39 +00:00
configure.in	Add the tgt-vvp code generator target.	2001-03-19 01:20:46 +00:00
eval_expr.c	VVP support for memories in expressions,	2001-05-10 00:26:53 +00:00
vvp.c	Support marking vvp interpreter (Stephan Boettcher)	2001-04-28 20:06:07 +00:00
vvp_priv.h	Behavioral code to read memories. (Stephan Boettcher)	2001-05-06 17:54:33 +00:00
vvp_process.c	VVP support for memories in expressions,	2001-05-10 00:26:53 +00:00
vvp_scope.c	Fixup the resolver syntax.	2001-05-12 16:34:47 +00:00

README.txt

THE VVP TARGET

SYMBOL NAME CONVENTIONS

There are some naming conventions that the vp target uses for
generating symbol names.

* wires and regs

Nets and variables are named V_<full-name> where <full-name> is the
full hierarchical name of the signal.

* Logic devices

Logic devices (and, or, buf, bufz, etc.) are named L_<full_name>. In
this case the symbol is attached to a functor that is the output of
the logic device.