iverilog/tgt-vvp
steve 41ce198a1f add XOR support. 2001-04-15 16:37:48 +00:00
..
.cvsignore Add the tgt-vvp code generator target. 2001-03-19 01:20:46 +00:00
Makefile.in Fix compilation warnings. 2001-03-31 19:29:23 +00:00
README.txt Add a README for notes about the vvp target. 2001-03-25 18:10:39 +00:00
configure.in Add the tgt-vvp code generator target. 2001-03-19 01:20:46 +00:00
eval_expr.c add XOR support. 2001-04-15 16:37:48 +00:00
vvp.c Support error code from target_t::end_design method. 2001-03-27 03:31:06 +00:00
vvp_priv.h Generate vvp code for functions with ports. 2001-04-06 02:28:02 +00:00
vvp_process.c vvp support for <= with internal delay. 2001-04-15 02:58:11 +00:00
vvp_scope.c add XOR support. 2001-04-15 16:37:48 +00:00

README.txt

THE VVP TARGET

SYMBOL NAME CONVENTIONS

There are some naming conventions that the vp target uses for
generating symbol names.

* wires and regs

Nets and variables are named V_<full-name> where <full-name> is the
full hierarchical name of the signal.

* Logic devices

Logic devices (and, or, buf, bufz, etc.) are named L_<full_name>. In
this case the symbol is attached to a functor that is the output of
the logic device.