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Lars-Peter Clausen
9ffe627b32
Check that the var keyword is supported in the following contexts * Module ports (both ANSI and non-ANSI) * Module variable declarations * Package variable declarations * Task and function ports * block variable declarations * for loop variable declarations Also check that it is an error to use the var keyword in a for loop without an explicit data type, as that is not allowed by the standard. Signed-off-by: Lars-Peter Clausen <[email protected]>
42 lines
727 B
Verilog
42 lines
727 B
Verilog
// Check that the var keyword is supported for function ports
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`define check(val, exp) \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, `"val`", val, exp); \
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return 1'b1; \
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end \
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return 1'b0;
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module test;
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function bit f1 (var int x);
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`check(x, 10)
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endfunction
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function bit f2 (input var int x);
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`check(x, 20)
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endfunction
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function bit f3 (var [7:0] x);
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`check(x, 30)
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endfunction
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function bit f4 (input var [7:0] x);
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`check(x, 40)
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endfunction
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initial begin
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bit failed;
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failed = f1(10);
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failed |= f2(20);
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failed |= f3(30);
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failed |= f4(40);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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