mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-29 01:03:29 +02:00
Lars-Peter Clausen
4c9af1c47a
Check that it is possible to declare the type separately from the direction for non-ANSI integer, time and atom2 ports. Check that it is possible to both declare the type before and after the direction. For integer, time and atom2 types the range specification on the port direction declaration should be empty, rather than the implicit packed dimension of the integer type. Signed-off-by: Lars-Peter Clausen <[email protected]>
17 lines
345 B
Verilog
17 lines
345 B
Verilog
// Check that it is possible to declare the data type for an integer type module
|
|
// port before the direction for non-ANSI style port declarations.
|
|
|
|
module test(x);
|
|
integer x;
|
|
output x;
|
|
|
|
initial begin
|
|
if ($bits(x) == $bits(integer)) begin
|
|
$display("PASSED");
|
|
end else begin
|
|
$display("FAILED");
|
|
end
|
|
end
|
|
|
|
endmodule
|