mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-29 01:03:29 +02:00
Stephen Williams
7b102b18fd
This patch is based on one from "bruce <[email protected]>". I've applied all but the elaboration code, which I rewrote to properly work with the elaboration work queue. I also constrained the implementation so that the parameter name must have exactly two components: the root scope name and the parameter name. This is necessary to keep the defparm processing sane. The comments from bruce's original patch are as follows: -- This patch would provide function to define parameter from command line. This serves the same functionality as 'defparam' in Verilog source code, but provide much more ease for using. Parameter definition can be write in command file, with following syntax: +parameter+<scope>.<parameter>=<val> *Do not apply any space between them* The scope name should be full hierachical name with root name at the begining. The following example would override test.T1 with new value 2'b01: +parameter+test.T1=2'b01 'test' here is the root module name. The parameter value here should be constant. Parameter definition can also be write in the command line: iverilog -Ptest.T1=2'b01 This serves the same functionality with the previous example. If we define the same parameter in command file and command line, the one in command line would over-write all others.
109 lines
2.6 KiB
C++
109 lines
2.6 KiB
C++
/*
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* Copyright (c) 1998-2009 Stephen Williams ([email protected])
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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# include "config.h"
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# include "Module.h"
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# include "PGate.h"
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# include "PWire.h"
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# include <assert.h>
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list<Module::named_expr_t> Module::user_defparms;
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/* n is a permallocated string. */
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Module::Module(perm_string n)
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: PScope(n)
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{
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library_flag = false;
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is_cell = false;
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uc_drive = UCD_NONE;
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default_nettype = NetNet::NONE;
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timescale_warn_done = false;
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}
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Module::~Module()
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{
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}
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void Module::add_gate(PGate*gate)
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{
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gates_.push_back(gate);
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}
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unsigned Module::port_count() const
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{
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return ports.size();
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}
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/*
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* Return the array of PEIdent object that are at this port of the
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* module. If the port is internally unconnected, return an empty
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* array.
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*/
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const vector<PEIdent*>& Module::get_port(unsigned idx) const
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{
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assert(idx < ports.size());
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static const vector<PEIdent*> zero;
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if (ports[idx])
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return ports[idx]->expr;
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else
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return zero;
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}
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unsigned Module::find_port(const char*name) const
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{
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assert(name != 0);
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for (unsigned idx = 0 ; idx < ports.size() ; idx += 1) {
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if (ports[idx] == 0) {
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/* It is possible to have undeclared ports. These
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are ports that are skipped in the declaration,
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for example like so: module foo(x ,, y); The
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port between x and y is unnamed and thus
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inaccessible to binding by name. */
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continue;
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}
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assert(ports[idx]);
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if (ports[idx]->name == name)
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return idx;
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}
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return ports.size();
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}
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PGate* Module::get_gate(perm_string name)
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{
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for (list<PGate*>::iterator cur = gates_.begin()
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; cur != gates_.end()
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; cur ++ ) {
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if ((*cur)->get_name() == name)
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return *cur;
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}
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return 0;
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}
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const list<PGate*>& Module::get_gates() const
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{
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return gates_;
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}
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