When you have an expression like this (extreme example): a[idx[1]][idx[2]*4 +: 4] <= #(idx[3]) 4'ha; where a is a reg array and idx is a reg or net array. The retrieval of idx[2] was clobbering index register 3, which was set before evaluating the part offset expression, then used in the %set/av of the array value. (likewise for idx[1] and idx[3]]) To avoid this issue, this patch adds and uses a new instruction %ix/mov which simply copies one indexed register to another. When necessary, expressions are first evaluated into temporary registers to avoid clobbering, then moved in to place before the %*/av instruction. |
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| .. | ||
| Makefile.in | ||
| README.txt | ||
| draw_class.c | ||
| draw_enum.c | ||
| draw_mux.c | ||
| draw_net_input.c | ||
| draw_switch.c | ||
| draw_ufunc.c | ||
| draw_vpi.c | ||
| eval_bool.c | ||
| eval_expr.c | ||
| eval_object.c | ||
| eval_real.c | ||
| eval_string.c | ||
| modpath.c | ||
| stmt_assign.c | ||
| vector.c | ||
| vvp-s.conf.in | ||
| vvp.c | ||
| vvp.conf.in | ||
| vvp_config.h.in | ||
| vvp_priv.h | ||
| vvp_process.c | ||
| vvp_scope.c | ||
README.txt
THE VVP TARGET SYMBOL NAME CONVENTIONS There are some naming conventions that the vp target uses for generating symbol names. * wires and regs Nets and variables are named V_<full-name> where <full-name> is the full hierarchical name of the signal. * Logic devices Logic devices (and, or, buf, bufz, etc.) are named L_<full_name>. In this case the symbol is attached to a functor that is the output of the logic device. GENERAL FUNCTOR WEB STRUCTURE The net of gates, signals and resolvers is formed from the input design. The basic structure is wrapped around the nexus, which is represented by the ivl_nexus_t. Each nexus represents a resolved value. The input of the nexus is fed by a single driver. If the nexus in the design has multiple drivers, the drivers are first fed into a resolver (or a tree of resolvers) to form a single output that is the nexus. The nexus, then, feeds its output to the inputs of other gates, or to the .net objects in the design.