iverilog/tgt-vvp
Jared Casper 51ca2d1243 Fix using array elements in expressions with an array element lval.
When you have an expression like this (extreme example):

a[idx[1]][idx[2]*4 +: 4] <= #(idx[3]) 4'ha;

where a is a reg array and idx is a reg or net array.  The retrieval
of idx[2] was clobbering index register 3, which was set before
evaluating the part offset expression, then used in the %set/av of the
array value.  (likewise for idx[1] and idx[3]])

To avoid this issue, this patch adds and uses a new instruction
%ix/mov which simply copies one indexed register to another.  When
necessary, expressions are first evaluated into temporary registers to
avoid clobbering, then moved in to place before the %*/av instruction.
2013-10-07 16:47:50 -07:00
..
Makefile.in Draft run-time support for SystemVerilog class objects. 2012-12-10 19:20:02 -08:00
README.txt tgt-vvp generates code that skips nets as inputs. 2001-08-10 00:40:45 +00:00
draw_class.c Add support for darrays as class properties. 2013-01-27 20:10:25 -08:00
draw_enum.c updated FSF-address 2012-08-29 10:12:10 -07:00
draw_mux.c Fix printf opcode argument mismatches in tgt-vvp (cppcheck) 2012-08-31 12:36:55 -07:00
draw_net_input.c PV-to-concat belnding should use a strength-aware concat. 2013-02-02 10:44:16 -08:00
draw_switch.c updated FSF-address 2012-08-29 10:12:10 -07:00
draw_ufunc.c Handle strings as arguments to automatic functions. 2013-09-20 20:44:56 -07:00
draw_vpi.c Fix uninitialized buffer when drawing a real VPI argument 2013-01-22 09:22:50 -08:00
eval_bool.c updated FSF-address 2012-08-29 10:12:10 -07:00
eval_expr.c Fix print token/argument mismatches and other cppcheck fixes 2013-09-09 13:34:38 -07:00
eval_object.c Code generation and runtime for class shallow copy. 2013-04-28 10:10:36 -07:00
eval_real.c Handle real value class properties. 2013-01-27 20:10:25 -08:00
eval_string.c Handle strings as class object properties. 2013-01-27 20:10:25 -08:00
modpath.c updated FSF-address 2012-08-29 10:12:10 -07:00
stmt_assign.c Fix using array elements in expressions with an array element lval. 2013-10-07 16:47:50 -07:00
vector.c updated FSF-address 2012-08-29 10:12:10 -07:00
vvp-s.conf.in Remove redundant back-end selections. 2008-09-07 16:43:54 -07:00
vvp.c updated FSF-address 2012-08-29 10:12:10 -07:00
vvp.conf.in Remove redundant back-end selections. 2008-09-07 16:43:54 -07:00
vvp_config.h.in updated FSF-address 2012-08-29 10:12:10 -07:00
vvp_priv.h Implement class constructors. 2013-04-20 16:38:35 -07:00
vvp_process.c Fix using array elements in expressions with an array element lval. 2013-10-07 16:47:50 -07:00
vvp_scope.c vvp code generation for class methods in class scope. 2013-03-24 15:12:35 -07:00

README.txt

THE VVP TARGET

SYMBOL NAME CONVENTIONS

There are some naming conventions that the vp target uses for
generating symbol names.

* wires and regs

Nets and variables are named V_<full-name> where <full-name> is the
full hierarchical name of the signal.

* Logic devices

Logic devices (and, or, buf, bufz, etc.) are named L_<full_name>. In
this case the symbol is attached to a functor that is the output of
the logic device.


GENERAL FUNCTOR WEB STRUCTURE

The net of gates, signals and resolvers is formed from the input
design. The basic structure is wrapped around the nexus, which is
represented by the ivl_nexus_t.

Each nexus represents a resolved value. The input of the nexus is fed
by a single driver. If the nexus in the design has multiple drivers,
the drivers are first fed into a resolver (or a tree of resolvers) to
form a single output that is the nexus.

The nexus, then, feeds its output to the inputs of other gates, or to
the .net objects in the design.