luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
iverilog/vhdlpp
History
Pawel Szostek 13519ab5c7 Soft treating of multiple architectures in VHDL 
In VHDL it is allowed to have multiple architectures
per one entity. The proper architecture should be then
chosen in a configuration block. Now, if many architectures
will be found, then there will be a warning message printed.
FIXME notes are added in order not to forget about changes to
be done
 		2011-03-23 11:45:33 -07:00
..
Makefile.in Parse component declarations / parse signal declarations. 2011-03-22 09:18:20 -07:00
README.txt Create an Architecture class and bind them to their entities. 2011-02-13 16:43:04 -08:00
architec.cc Parse component declarations / parse signal declarations. 2011-03-22 09:18:20 -07:00
architec.h Parse component declarations / parse signal declarations. 2011-03-22 09:18:20 -07:00
architec_emit.cc Code generator for architectures. 2011-02-13 16:48:52 -08:00
compiler.cc Add file/line information to entities and ports 2011-01-18 17:03:51 -08:00
compiler.h Add file/line information to entities and ports 2011-01-18 17:03:51 -08:00
debug.cc Parse component declarations / parse signal declarations. 2011-03-22 09:18:20 -07:00
entity.cc Parse component declarations / parse signal declarations. 2011-03-22 09:18:20 -07:00
entity.h Parse component declarations / parse signal declarations. 2011-03-22 09:18:20 -07:00
entity_elaborate.cc Soft treating of multiple architectures in VHDL 2011-03-23 11:45:33 -07:00
entity_emit.cc Parse component declarations / parse signal declarations. 2011-03-22 09:18:20 -07:00
expression.cc Add support for unary abs and not operators. 2011-02-20 17:03:46 -08:00
expression.h Add support for unary abs and not operators. 2011-02-20 17:03:46 -08:00
expression_emit.cc Add support for unary abs and not operators. 2011-02-20 17:03:46 -08:00
lexor.lex Merge branch 'master' into work4 2011-03-14 17:34:57 -07:00
lexor_keyword.gperf Fix remaining space issues. 2011-03-14 16:26:31 -07:00
main.cc Parse component declarations / parse signal declarations. 2011-03-22 09:18:20 -07:00
parse.y Parse component declarations / parse signal declarations. 2011-03-22 09:18:20 -07:00
parse_api.h Add parser support for architecture declaratives and component instantiations 2011-03-22 09:18:01 -07:00
parse_misc.cc Soft treating of multiple architectures in VHDL 2011-03-23 11:45:33 -07:00
parse_misc.h Stub support for "use" directives. 2011-02-19 13:08:26 -08:00
parse_wrap.h Do type mapping in the parser. 2011-02-13 16:54:56 -08:00
vhdlint.cc Merge branch 'master' into work4 2011-03-14 17:34:57 -07:00
vhdlint.h Fix spacing problems. 2011-03-03 11:21:31 -08:00
vhdlnum.h Introductory changes for numbers handling 2011-02-10 18:34:13 -08:00
vhdlpp_config.h.in Introduce shell of vhdlpp program. 2011-01-18 17:03:51 -08:00
vhdlreal.cc Fix spacing problems. 2011-03-03 11:21:31 -08:00
vhdlreal.h Fix spacing problems. 2011-03-03 11:21:31 -08:00
vsignal.cc Parse component declarations / parse signal declarations. 2011-03-22 09:18:20 -07:00
vsignal.h Parse component declarations / parse signal declarations. 2011-03-22 09:18:20 -07:00
vtype.cc Handle signed stdlogic. 2011-02-27 10:33:37 -08:00
vtype.h Handle signed vs unsigned vector types. 2011-02-25 20:09:31 -08:00

README.txt 

vhdlpp COMMAND LINE FLAGS:

-D <token>
  Debug flags. The token can be

  * yydebug | no-yydebug

  * entities=<path>

-V
  Display version on stdout

-v
  Verbose: Display version on stderr, and enable verbose messages to
  stderr.