59 lines
1.5 KiB
Verilog
59 lines
1.5 KiB
Verilog
// Check that null-bytes are handled consistently between string literals,
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// number literals and signals of all kinds, especially when formatting as a
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// string.
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module test;
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reg failed = 1'b0;
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`define check(val, exp) \
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if (val != exp) begin \
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$display("FAILED(%0d): Expected '%0s', got '%0s'.", `__LINE__, exp, val); \
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failed = 1'b1; \
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end
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reg [255:0] s;
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reg [31:0] x;
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reg [31:0] y[1:0];
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wire [31:0] z;
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wire [31:0] w;
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assign z = "\000a\000b";
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assign w = 32'h00610062;
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initial begin
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$sformat(s, ":%x:%0x:%s:%0s:", "\000a\000b", "\000a\000b", "\000a\000b", "\000a\000b");
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`check(s, ":00610062:610062: a b:a b:")
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$sformat(s, ":%x:%0x:%s:%0s:", 32'h00610062, 32'h00610062, 32'h00610062, 32'h00610062);
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`check(s, ":00610062:610062: a b:a b:")
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x = "\000a\000b";
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$sformat(s, ":%x:%0x:%s:%0s:", x, x, x, x);
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`check(s, ":00610062:610062: a b:a b:")
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x = 32'h00610062;
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$sformat(s, ":%x:%0x:%s:%0s:", x, x, x, x);
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`check(s, ":00610062:610062: a b:a b:")
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y[0] = "\000a\000b";
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$sformat(s, ":%x:%0x:%s:%0s:", y[0], y[0], y[0], y[0]);
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`check(s, ":00610062:610062: a b:a b:")
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y[1] = 32'h00610062;
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$sformat(s, ":%x:%0x:%s:%0s:", y[1], y[1], y[1], y[1]);
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`check(s, ":00610062:610062: a b:a b:")
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$sformat(s, ":%x:%0x:%s:%0s:", z, z, z, z);
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`check(s, ":00610062:610062: a b:a b:")
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$sformat(s, ":%x:%0x:%s:%0s:", w, w, w, w);
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`check(s, ":00610062:610062: a b:a b:")
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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