iverilog/tgt-pcb
Martin Whitaker b988543096 Use GNU make pattern rules to handle multiple file output from bison.
With a pattern rule, the recipe will only be executed once, even when
the rule has multiple targets. Using this to handle the output from
bison is included as an example in the GNU make manual.

This fixes the makefiles so that bison-generated header files will be
regenerated if they are deleted.
2020-08-17 17:03:57 +01:00
..
Makefile.in Use GNU make pattern rules to handle multiple file output from bison. 2020-08-17 17:03:57 +01:00
cppcheck.sup Remove some cppcheck warnings 2014-06-28 16:56:09 -07:00
footprint.cc Spelling fixes 2014-01-30 15:34:20 -08:00
fp.lex Update flex destroy to work for version 2.6 and greater 2017-11-16 19:17:50 -08:00
fp.y Remove bison warning and make YACC rule match the rest 2015-04-30 10:12:57 -07:00
fp_api.h Update header files to use a more standard name to prevent rereading 2014-07-23 13:42:56 -07:00
pcb-s.conf Add a pcb-s.conf file compatible with the -S flag. 2011-12-24 10:39:41 -05:00
pcb.cc Merge branch 'master' of github.com:steveicarus/iverilog 2012-12-23 12:18:05 -08:00
pcb.conf Introduce PCB code generator. 2011-12-20 14:16:54 -06:00
pcb_config.h.in Update header files to use a more standard name to prevent rereading 2014-07-23 13:42:56 -07:00
pcb_priv.h Update header files to use a more standard name to prevent rereading 2014-07-23 13:42:56 -07:00
scope.cc Add CXX warning flag to tgt-pcb and tgt-vhdl and fix warnings 2013-07-11 17:40:57 -07:00
show_netlist.cc updated FSF-address 2012-08-29 10:12:10 -07:00
show_pcb.cc Merge branch 'master' of github.com:steveicarus/iverilog 2012-12-23 12:18:05 -08:00