40 lines
1.3 KiB
Plaintext
40 lines
1.3 KiB
Plaintext
:ivl_version "13.0" "vec4-stack";
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:vpi_module "system";
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; Copyright (c) 2001-2015 Stephen Williams (steve@icarus.com)
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;
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; This program is free software; you can redistribute it and/or modify
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; it under the terms of the GNU General Public License as published by
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; the Free Software Foundation; either version 2 of the License, or
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; (at your option) any later version.
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;
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; This program is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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;
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; You should have received a copy of the GNU General Public License along
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; with this program; if not, write to the Free Software Foundation, Inc.,
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; 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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; This example is similar to the code that the following Verilog program
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; would generate:
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;
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; module main;
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; initial $display("Hello, World.");
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; endmodule
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;
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; This tests that a simple %vpi_call works properly. This is very nearly
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; the most trivial VVP source file that can generate any output.
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main .scope module, "main" "main" 0 0;
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code %vpi_call 0 0 "$display", "Hello, World." {0 0 0};
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%end;
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.thread code;
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:file_names 2;
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"N/A";
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"<interactive>";
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