iverilog/vvp/examples/hello.vvp

:ivl_version "13.0" "vec4-stack";
:vpi_module "system";

; Copyright (c) 2001-2015  Stephen Williams (steve@icarus.com)
;
;    This program is free software; you can redistribute it and/or modify
;    it under the terms of the GNU General Public License as published by
;    the Free Software Foundation; either version 2 of the License, or
;    (at your option) any later version.
;
;    This program is distributed in the hope that it will be useful,
;    but WITHOUT ANY WARRANTY; without even the implied warranty of
;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;    GNU General Public License for more details.
;
;    You should have received a copy of the GNU General Public License along
;    with this program; if not, write to the Free Software Foundation, Inc.,
;    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.


; This example is similar to the code that the following Verilog program
; would generate:
;
;    module main;
;       initial $display("Hello, World.");
;    endmodule
;
; This tests that a simple %vpi_call works properly. This is very nearly
; the most trivial VVP source file that can generate any output.


main	.scope module, "main" "main" 0 0;

code	%vpi_call 0 0 "$display", "Hello, World." {0 0 0};
	%end;
	.thread	code;
:file_names 2;
    "N/A";
    "<interactive>";