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<div class="globaltoc" data-expand-depth="0"><p class="caption" role="heading" aria-level="3"><span class="caption-text">Contents:</span></p>
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<li class="toctree-l1"><a class="reference internal" href="../releases/index.html">Icarus Verilog Release Notes</a><ul>
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<li class="toctree-l2"><a class="reference internal" href="../releases/v13-0-release-note.html">🎉 Release V13.0</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../usage/installation.html">Installation Guide</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../usage/getting_started.html">Getting Started With Icarus Verilog</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../usage/simulation.html">Simulation Using Icarus Verilog</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../usage/command_line_flags.html">iverilog Command Line Flags</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../usage/command_files.html">Command File Format</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../usage/verilog_attributes.html">Verilog Attributes</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../usage/ivlpp_flags.html">IVLPP - IVL Preprocessor</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../usage/vvp_flags.html">VVP Command Line Flags</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../usage/vvp_debug.html">VVP Interactive Mode</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../usage/vvp_library.html">VVP as a library</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../usage/vhdlpp_flags.html">vhdlpp Command Line Flags</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../usage/waveform_viewer.html">Viewing Waveforms</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../usage/vpi.html">Using VPI</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../usage/icarus_verilog_extensions.html">Icarus Verilog Extensions</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../usage/icarus_verilog_quirks.html">Icarus Verilog Quirks</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../usage/reporting_issues.html">Reporting Issues</a></li>
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</ul>
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</li>
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<li class="toctree-l1"><a class="reference internal" href="../targets/index.html">The Icarus Verilog Targets</a><ul>
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<li class="toctree-l2"><a class="reference internal" href="../targets/tgt-vvp.html">The vvp Code Generator (-tvvp)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../targets/tgt-stub.html">The stub Code Generator (-tstub)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../targets/tgt-null.html">The null Code Generator (-tnull)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../targets/tgt-vhdl.html">The VHDL Code Generator (-tvhdl)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../targets/tgt-vlog95.html">The Verilog ‘95 Code Generator (-tvlog95)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../targets/tgt-pcb.html">The PCB Code Generator (-tpcb)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../targets/tgt-fpga.html">The FPGA Code Generator (-tfpga)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../targets/tgt-pal.html">The PAL Code Generator (-tpal)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../targets/tgt-sizer.html">The sizer Code Analyzer (-tsizer)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../targets/tgt-verilog.html">The Verilog Code Generator (-tverilog)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../targets/tgt-blif.html">The BLIF Code Generator (-tblif)</a></li>
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</ul>
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<li class="toctree-l1 current"><a class="reference internal" href="index.html">Icarus Verilog Developer Support</a><ul class="current">
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<li class="toctree-l2"><a class="reference internal" href="getting_started.html">Getting Started as a Contributor</a></li>
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<li class="toctree-l2"><a class="reference internal" href="regression_tests.html">The Regression Test Suite</a></li>
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<li class="toctree-l4"><a class="reference internal" href="guide/ivl/netlist.html">Netlist Format</a></li>
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<li class="toctree-l4"><a class="reference internal" href="guide/ivl/attributes.html">Icarus Verilog Attributes</a></li>
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<li class="toctree-l4"><a class="reference internal" href="guide/ivl/ivl_target.html">Loadable Target API (ivl_target)</a></li>
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<li class="toctree-l4"><a class="reference internal" href="guide/ivl/lpm.html">What Is LPM</a></li>
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<li class="toctree-l4"><a class="reference internal" href="guide/ivl/t-dll.html">Loadable Targets</a></li>
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</ul>
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<li class="toctree-l3"><a class="reference internal" href="guide/vvp/index.html">VVP - Verilog Virtual Processor</a><ul>
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<li class="toctree-l4"><a class="reference internal" href="guide/vvp/opcodes.html">Executable Instruction Opcodes</a></li>
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<li class="toctree-l4"><a class="reference internal" href="guide/vvp/vpi.html">VPI Within VVP</a></li>
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<li class="toctree-l4"><a class="reference internal" href="guide/vvp/vthread.html">Thread Details</a></li>
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<li class="toctree-l4"><a class="reference internal" href="guide/vvp/debug.html">Debug Aids For VVP</a></li>
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</ul>
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<li class="toctree-l3"><a class="reference internal" href="guide/tgt-vvp/tgt-vvp.html">The VVP Target</a></li>
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<li class="toctree-l3"><a class="reference internal" href="guide/vpi/index.html">VPI in Icarus Verilog</a><ul>
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<li class="toctree-l4"><a class="reference internal" href="guide/vpi/vpi.html">VPI Modules in Icarus Verilog</a></li>
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<li class="toctree-l4"><a class="reference internal" href="guide/vpi/va_math.html">Verilog-A math library</a></li>
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</ul>
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<li class="toctree-l3"><a class="reference internal" href="guide/cadpli/cadpli.html">Cadence PLI1 Modules</a></li>
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<li class="toctree-l3"><a class="reference internal" href="guide/misc/index.html">Miscellaneous</a><ul>
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<li class="toctree-l4"><a class="reference internal" href="guide/misc/ieee1364-notes.html">IEEE1364 Notes</a></li>
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<li class="toctree-l4"><a class="reference internal" href="guide/misc/swift.html">Swift Model Support (Preliminary)</a></li>
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<li class="toctree-l2 current"><a class="current reference internal" href="#">Glossary</a></li>
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<section id="glossary">
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<h1>Glossary<a class="headerlink" href="#glossary" title="Link to this heading">¶</a></h1>
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<p>Throughout Icarus Verilog descriptions and source code, I use a
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variety of terms and acronyms that might be specific to Icarus
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Verilog, have an Icarus Verilog specific meaning, or just aren’t
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widely known. So here I define these terms.</p>
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<dl class="simple">
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<dt>LRM - Language Reference Manual</dt><dd><p>This is a generic acronym, but in the Verilog world we sometimes
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mean <em>the</em> language reference manual, the IEEE1364 standard.</p>
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</dd>
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<dt>PLI - Programming Language Interface</dt><dd><p>This is a C API into Verilog simulators that is defined by the
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IEEE1364. There are two major interfaces, sometimes called PLI 1
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and PLI 2. PLI 2 is also often called VPI.</p>
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</dd>
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<dt>UDP - User Defined Primitive</dt><dd><p>These are objects that Verilog programmers define with the
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“primitive” keyword. They are truth-table based devices. The
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syntax for defining them is described in the LRM.</p>
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</dd>
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<dt>VPI - Verilog Procedural Interface</dt><dd><p>This is the C API that is defined by the Verilog standard, and
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that Icarus Verilog partially implements. See also PLI.</p>
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</dd>
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<dt>VVM - Verilog Virtual Machine</dt><dd><p>This is the Icarus Verilog runtime that works with the code
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generator that generates C++.</p>
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</dd>
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<dt>VVP - Verilog Virtual Processor</dt><dd><p>This is the Icarus Verilog runtime that reads in custom code in a
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form that I call “VVP Assembly”.</p>
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</dd>
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<dt>LPM - Library of Parameterized Modules</dt><dd><p>LPM (Library of Parameterized Modules) is EIS-IS standard 103-A. It is
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a standard library of abstract devices that are designed to be close
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enough to the target hardware to be easily translated, yet abstract
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enough to support a variety of target technologies without excessive
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constraints. Icarus Verilog uses LPM internally to represent idealized
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hardware, especially when doing target neutral synthesis.</p>
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</dd>
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</dl>
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</section>
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