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150 lines
5.8 KiB
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<!DOCTYPE html>
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<html lang="en" data-content_root="../">
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<title>Glossary — Icarus Verilog documentation</title>
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<div class="body" role="main">
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<section id="glossary">
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<h1>Glossary<a class="headerlink" href="#glossary" title="Link to this heading">¶</a></h1>
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<p>Throughout Icarus Verilog descriptions and source code, I use a
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variety of terms and acronyms that might be specific to Icarus
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Verilog, have an Icarus Verilog specific meaning, or just aren’t
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widely known. So here I define these terms.</p>
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<dl class="simple">
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<dt>LRM - Language Reference Manual</dt><dd><p>This is a generic acronym, but in the Verilog world we sometimes
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mean <em>the</em> language reference manual, the IEEE1364 standard.</p>
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</dd>
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<dt>PLI - Programming Language Interface</dt><dd><p>This is a C API into Verilog simulators that is defined by the
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IEEE1364. There are two major interfaces, sometimes called PLI 1
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and PLI 2. PLI 2 is also often called VPI.</p>
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</dd>
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<dt>UDP - User Defined Primitive</dt><dd><p>These are objects that Verilog programmers define with the
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“primitive” keyword. They are truth-table based devices. The
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syntax for defining them is described in the LRM.</p>
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</dd>
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<dt>VPI - Verilog Procedural Interface</dt><dd><p>This is the C API that is defined by the Verilog standard, and
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that Icarus Verilog partially implements. See also PLI.</p>
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</dd>
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<dt>VVM - Verilog Virtual Machine</dt><dd><p>This is the Icarus Verilog runtime that works with the code
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generator that generates C++.</p>
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</dd>
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<dt>VVP - Verilog Virtual Processor</dt><dd><p>This is the Icarus Verilog runtime that reads in custom code in a
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form that I call “VVP Assembly”.</p>
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</dd>
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<dt>LPM - Library of Parameterized Modules</dt><dd><p>LPM (Library of Parameterized Modules) is EIS-IS standard 103-A. It is
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a standard library of abstract devices that are designed to be close
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enough to the target hardware to be easily translated, yet abstract
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enough to support a variety of target technologies without excessive
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constraints. Icarus Verilog uses LPM internally to represent idealized
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hardware, especially when doing target neutral synthesis.</p>
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</dd>
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</dl>
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</section>
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</div>
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</div>
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</div>
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<div class="sphinxsidebar" role="navigation" aria-label="main navigation">
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<div class="sphinxsidebarwrapper">
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<h1 class="logo"><a href="../index.html">Icarus Verilog</a></h1>
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<h3>Navigation</h3>
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<p class="caption" role="heading"><span class="caption-text">Contents:</span></p>
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<ul class="current">
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<li class="toctree-l1"><a class="reference internal" href="../usage/index.html">Icarus Verilog Usage</a></li>
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<li class="toctree-l1"><a class="reference internal" href="../targets/index.html">The Icarus Verilog Targets</a></li>
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<li class="toctree-l1 current"><a class="reference internal" href="index.html">Icarus Verilog Developer Support</a><ul class="current">
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<li class="toctree-l2"><a class="reference internal" href="getting_started.html">Getting Started as a Contributor</a></li>
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<li class="toctree-l2"><a class="reference internal" href="regression_tests.html">The Regression Test Suite</a></li>
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<li class="toctree-l2"><a class="reference internal" href="version_stamps.html">Files With Version Information</a></li>
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<li class="toctree-l2"><a class="reference internal" href="guide/index.html">Developer Guide</a></li>
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<li class="toctree-l2 current"><a class="current reference internal" href="#">Glossary</a></li>
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</ul>
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</li>
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</ul>
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<div class="relations">
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<h3>Related Topics</h3>
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<ul>
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<li><a href="../index.html">Documentation overview</a><ul>
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<li><a href="index.html">Icarus Verilog Developer Support</a><ul>
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<li>Previous: <a href="guide/misc/xilinx-hint.html" title="previous chapter">Xilinx Hint</a></li>
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©2024-2025, Stephen Williams.
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<a href="../_sources/developer/glossary.rst.txt"
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rel="nofollow">Page source</a>
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