3 Commits

Author	SHA1	Message	Date
Nick Gasson	8189c4ee43	Generate VHDL entities and architectures for all module scopes	2008-05-31 15:28:25 +01:00
Nick Gasson	e38494a10c	Pretty-print VHDL output	2008-05-29 16:24:16 +01:00
Nick Gasson	bfa2bfc8ae	Makefile and autoconf changes to build VHDL code generator	2008-05-28 17:17:39 +01:00