Commit Graph

14 Commits

Author SHA1 Message Date
Cary R d98c925f53 Some compiler cleanup and minor memory leak fixes.
This patch cleans up some unneeded code. Releases some allocated
memory before the compiler quits and fixes a couple minor memory
leaks in the compiler and vvp code generator.
2009-06-19 21:42:07 -07:00
Cary R d06f6dfc51 Add support for unconnected_drive.
Icarus has recognized this directive, but it did not do anything
with the information. This patch adds the functionality for most
common cases. It adds this by changing the input net type from
wire/tri to tri1 or tri0 depending on the pull. The issue is that
if the input net is not a wire or tri this is not safe and should
really be done as an external pull gate connected to the input.
We will need to handle this is it ever comes up. For now a sorry
message is printed.
2009-06-07 16:14:52 -07:00
Cary R 636758f66d Add support for `celldefine, vpiCellInstance
This patch adds real functionality for `celldefine and pushes this
property to the run time which can access this with vpiCellInstance.
This is technically only available for a module, but all scopes
have the property and only modules should return true when the
'endmodule' is between a `celldefine and `endcelldefine directive.
2009-05-23 14:13:47 -07:00
Stephen Williams bcaf7355ca Remove most of the lingering CVS droppings.
Remove the #ident and $Log$ strings from all the header files and
almost all of the C/C++ source files. I think it is better to get
this done all at once, then to wait for each of the files to be
touched and edited in unrelated patches.
2008-12-05 21:48:28 -08:00
Stephen Williams ce9fd0147f Detect and warn about anachronistic use of begin/end in generate.
Verilog-2001 only allows a single generate item within a generate-
endgenerate region, but allowed one to collect generate schemes with
begin/end blocks. Verilog-2005 cleaned up that mess, and it is the
2005 syntax that Icarus Verilog implements. This patch detects the
anachronistic use of begin/end within the generate region, ignores
the begin/end words, and prints a warning that the user is using an
obsolete syntax.
2008-06-18 20:33:30 -07:00
Stephen Williams 5b273178f5 Parse disciplines and contribution statements
Parse discipline declarations, net discipline declarations, and
analog contribution statements. Don't yet do anything useful with
these, just give a sorry message where they are encountered.
2008-05-11 12:00:11 -07:00
Cary R 676695c78f Check for extra digits in sized binary, octal and hex constants.
Print out a warning if extra digits are given for sized binary, octal
or hex constants. Decimal constants are very hard since we never
calculate the true number of bits the digits represent, so for now
decimal constants are not checked.
2007-10-18 10:12:20 -07:00
steve 1507dcd56d More C-like use of vlltype. 2003-03-08 20:58:18 +00:00
steve 7ad66b0725 Support old/new bison yylloc. 2002-11-03 20:36:53 +00:00
steve 52bf4e613f conditional ident string using autoconfig. 2002-08-12 01:34:58 +00:00
steve b734ecf02f Macintosh compilers do not support ident. 2000-02-23 02:56:53 +00:00
steve 46df679fc5 remove string from lexical phase. 1999-07-10 01:03:18 +00:00
steve b118634189 Handle procedural conditional, and some
of the conditional expressions.

 Elaborate signals and identifiers differently,
 allowing the netlist to hold signal information.
1998-11-07 17:05:05 +00:00
steve 3fb7a053be Introduce verilog to CVS. 1998-11-03 23:28:49 +00:00