de356b03c8
Fix most of the cppcheck warnings in the vhdlpp directory.
...
Mostly using size() vs empty() in the STL and a missing initialization.
2011-07-30 09:35:12 -07:00
836e61e878
Fix spacing issues in the code.
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Remove space at the end of line and space before tab since they serve
no purpose.
2011-07-30 09:33:28 -07:00
60deb775ca
Add support for VHDL's loop statements
2011-07-12 19:20:04 -07:00
ad31eaaea8
Add parser support for VHDL's procedure call
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Parse procedure calls and put them into
abstract syntax tree. Elaboration and emission
still has to be done.
2011-07-08 18:10:30 -07:00
5934dcc17c
Add parser support for vhdl's case-when
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Case-when statements are now recognized and
turned into corresponding objects. Elaboration
and emission is still not done.
2011-06-30 19:57:27 -07:00
bf40c8ecc5
Conditional statements and expressions
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Elaborate and emit a variety of conditional constructs.
Fix up type handling for some expression types
Elaborate continuous signal assignments.
2011-06-12 10:51:31 -07:00
da0fb1666f
Detect always @edge patterns
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VHDL doesn't have a direct way to express "always @(posedge...)"
statements, but we do want to detect common paradigms that naturally
translate. This makes for a better translation.
2011-05-28 10:49:33 -07:00
3e419dc854
Parse/decorate sequential statements.
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Get to the point where our sample program parses completely, and
the sequential statements generate SequentialStmt objects and a
process object in the architecture.
Also add a few missing expression types.
2011-05-08 16:40:35 -07:00
Cary R
Pawel Szostek
Stephen Williams