Stephen Williams
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5a6d07ff9f
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Emit Verilog stubs for entities
The verilog includes the module declaration with correct ports
in the correct order. Get the port directions correct.
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2011-01-18 17:03:51 -08:00 |
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Stephen Williams
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02820c9e34
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Parse create entities with ports
Create entity objects from entity declarations in the source,
and populate them with ports.
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2011-01-18 17:03:51 -08:00 |
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Stephen Williams
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8cf1fd1820
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Introduce shell of vhdlpp program.
Create the makefiles and configuration scripts to hold together
the vhdlpp front-end program. Create a shell main.
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2011-01-18 17:03:51 -08:00 |