0ca5a282e5
parse functions and tasks and delay value lists.
1999-05-30 03:12:56 +00:00
35893919e0
module parameter bind by name.
1999-05-29 02:36:17 +00:00
c1dbb56b70
Line number information.
1999-05-27 03:31:29 +00:00
0352864470
Much expression parsing work,
...
mark continuous assigns with source line info,
replace some assertion failures with Sorry messages.
1999-05-20 04:31:45 +00:00
10ffaeda90
Redo constant expression detection to happen
...
after parsing.
Parse more operators and expressions.
1999-05-16 05:08:42 +00:00
5de9b7c9f1
Parse and elaborate the concatenate operator
...
in structural contexts, Replace vector<PExpr*>
and list<PExpr*> with svector<PExpr*>, evaluate
constant expressions with parameters, handle
memories as lvalues.
Parse task declarations, integer types.
1999-05-10 00:16:57 +00:00
6625ea71c2
Parse more things.
1999-05-08 20:19:20 +00:00
8e73ff2376
Parse more complex continuous assign lvalues.
1999-05-07 04:26:49 +00:00
a568e526c6
Get rid of list<lgate> types.
1999-05-06 04:37:17 +00:00
b2b9097488
Parse more constant expressions.
1999-05-06 04:09:28 +00:00
10f46dae66
More intelligent selection of module to elaborate.
1999-05-05 03:27:14 +00:00
41f9a84a4b
Handle much more complex event expressions.
1999-05-01 02:57:52 +00:00
ce49708442
Parse OR of event expressions.
1999-04-29 02:16:26 +00:00
5895d3c98d
Add memories to the parse and elaboration phases.
1999-04-19 01:59:36 +00:00
bd40e5dfe1
Support sized decimal numbers,
...
Fix operator precedence order.
1999-03-16 04:44:45 +00:00
b7f833dd71
Support more operators, especially logical.
1999-03-15 02:43:32 +00:00
e2a37a8ccd
Add support for module parameters.
1999-02-21 17:01:57 +00:00
e5f5f41515
Elaborate gate ranges.
1999-02-15 02:06:15 +00:00
8bdd381cdf
Parse and elaborate the Verilog CASE statement.
1999-02-03 04:20:11 +00:00
fb439c78b9
Add the LineInfo class to carry the source file
...
location of things. PGate, Statement and PProcess.
elaborate handles module parameter mismatches,
missing or incorrect lvalues for procedural
assignment, and errors are propogated to the
top of the elaboration call tree.
Attach line numbers to processes, gates and
assignment statements.
1999-01-25 05:45:56 +00:00
2c1df3e6f7
Parse more UDP input edge descriptions.
1998-12-18 05:16:25 +00:00
10b345bd16
Fully elaborate Sequential UDP behavior.
1998-12-14 02:01:34 +00:00
e097c999d5
Elaborate UDP devices,
...
Support UDP type attributes, and
pass those attributes to nodes that
are instantiated by elaboration,
Put modules into a map instead of
a simple list.
1998-12-01 00:42:13 +00:00
91aad30e1f
Parse UDP primitives all the way to pform.
1998-11-25 02:35:53 +00:00
af8d6fbf01
NetAssign handles lvalues as pin links
...
instead of a signal pointer,
Wire attributes added,
Ability to parse UDP descriptions added,
XNF generates EXT records for signals with
the PAD attribute.
1998-11-23 00:20:22 +00:00
6b2fa19429
Handle while loops.
1998-11-11 03:13:04 +00:00
d27f260bc1
Check net ranges in declarations.
1998-11-11 00:01:51 +00:00
ebad845fc3
Add procedural while loops,
...
Parse procedural for loops,
Add procedural wait statements,
Add constant nodes,
Add XNOR logic gate,
Make vvm output look a bit prettier.
1998-11-09 18:55:33 +00:00
b118634189
Handle procedural conditional, and some
...
of the conditional expressions.
Elaborate signals and identifiers differently,
allowing the netlist to hold signal information.
1998-11-07 17:05:05 +00:00
3fb7a053be
Introduce verilog to CVS.
1998-11-03 23:28:49 +00:00
steve