bad8ed39c1
Parse VHDL subprogram bodies and return statements.
2012-11-03 09:54:07 -07:00
f5aafc32f9
updated FSF-address
2012-08-29 10:12:10 -07:00
8003382b3e
Elaborate and emit case statements.
2011-10-01 11:45:28 -07:00
f5220c54f1
Handle variables in process statements
...
Parse variables declared in the declaration section of process
statements, and support variable assignment statements.
2011-08-17 20:19:15 -07:00
60deb775ca
Add support for VHDL's loop statements
2011-07-12 19:20:04 -07:00
ad31eaaea8
Add parser support for VHDL's procedure call
...
Parse procedure calls and put them into
abstract syntax tree. Elaboration and emission
still has to be done.
2011-07-08 18:10:30 -07:00
5934dcc17c
Add parser support for vhdl's case-when
...
Case-when statements are now recognized and
turned into corresponding objects. Elaboration
and emission is still not done.
2011-06-30 19:57:27 -07:00
bf40c8ecc5
Conditional statements and expressions
...
Elaborate and emit a variety of conditional constructs.
Fix up type handling for some expression types
Elaborate continuous signal assignments.
2011-06-12 10:51:31 -07:00
fc25ccde06
Basic emit of sequential code
...
Infrastructure for debug and emit of sequential statements in processes.
This does not properly handle the actual semantics of the behavioral
code, but it provides an infrastructure where we can handle all the
tricky elaboration to come.
2011-05-15 11:07:42 -07:00
Stephen Williams
Arun Persaud
Pawel Szostek